Digital equipment develops continuously in context of the rapid development of electronic technology in recent years, and exhibits its uniqueness in fields of communication, navigation and so on. With the development of semiconductor devices, digital equipment is evolving towards integration and intelligence, and presents the features of high precision, high integration, versatility, human-machine interaction and programmability. Meanwhile, the development of semiconductor and integration has also promoted the innovation of digital technology, and the development of digital technology largely reflects the current level of electronics industry's development.
As a typical digital equipment, Pulse sequence generator has a great significance in the research of various fields. In traditional test field, especially for function test, noise tolerance test, signal jitter tolerance test of high-frequency circuit, high speed digital device and so on, the pulse signal with adjustable jitter frequency, variable jitter size and adjustable duty circle, which has rich frequencies is needed and sent to the system under test. Meanwhile, the testing signal with rich function modes is also needed to analyze and test the system under test to check its corresponding condition, running state and so on, or perform fault diagnosis.
In pulse sequence, jitter is a transient change's offset from its ideal position in short time. Jitter can be categorized into random jitter (RJ) and deterministic jitter (DJ). Moreover, the deterministic jitter can be further categorized into three types: period jitter (PJ), data-dependent jitter (DDJ) and duty-cycle dependent jitter (DCDJ).
The causes of random jitter are complex, and difficult to eliminate. Random jitter may be caused by device's internal thermal noise, crystal's random vibration, cosmic rays and so on. In addition, signal reflection, signal crosstalk, switching noise, power supply interference, EMI and so on will bring random jitters.
The clock system is a very critical part of the digital system, directly determines the success or failure of data transmission and reception, and is the aorta of the whole digital system. Therefore, the clock jitter has been a matter of great concern. The parameters regarding to the clock jitter is provided by chip's data sheet. As for the high-speed serial data, its transmission standards generally require that overall jitter, inherent jitter, random jitter etc. can't be too large under a specific bit error rate, such as 10−12. The most common methods used to quantify jitters are peak-to-peak jitter testing and root-mean-square jitter testing.
In a digital system, jitter will cause the system bit error rate (BER) to increase. In order to guarantee the performance of the digital system under the circumstance of jittering, the jitter should be limited to a certain range, which is called as jitter tolerance. Therefore, in order to measure the jitter tolerance of the digital system, it is necessary to simulate multi-type digital signal jitter or clock jitter for obtaining the maximum allowable range of jittering under the circumstance of guaranteeing the digital system's performance. However, the current methods used to quantify jitters is not suitable for the measurement of jitter tolerance, and as so far, there is no such test as adding jitters to the edges of a pulse sequence to measure the jitter tolerance.